The 2-Server system using Intilop’s UDP Offload Core and OpenCL™ implementing NASDAQ’s OPRA feed on Stratix V FPGA delivers unprecedented performance, reduced development time & accelerated Time ...

If you are looking at having to design a DDR3 interface and are contemplating using an FPGA to do it, check out the video demo on Altera’s site. There is a white paper you can download as well. DDR3 ...

Altera and Micron Technology announced on September 4 that the companies have jointly demonstrated successful interoperability between Altera Stratix V FPGAs and Micron's hybrid memory cube (HMC).