EDN

Clock randomization automated methodology to validate SoC designs

The demand for new and upgraded features is increasing day by day in modern semiconductors. This may include multiple power domains to support low power and full power modes and multiple clock domains ...
autoevolution

MTR Designs’ Ferrofluid Clock Will Bring a Touch of Awesome Into Your Office

If you’re into science and neat gadgets, maybe the Ferrofluid Clock from MTR Designs is the thing for you, as it manages to combine both into an elegant and unique timepiece that’s bound to become the ...
9to5google

Google on the difficulty of designing a 24-hour time picker

The Material Design team has an interesting blog post into what it calls the “24-hour Clock Design Challenge” that chronicles Google’s work creating a time picker for those that use a 24-hour format ...
EDN

Circuit simulation tool simplifies clock designs

Norwood, Mass. — Analog Devices Inc. claims engineers can now create complete, robust timing solutions in minutes with its ADIsimCLK clock IC design and simulation tool and three new clock ICs. The ...
Semiconductor Engineering

The Design Challenges Of Clock Integrity And Clock Jitter

Races, missed next-state values due to long paths, and metastability can result from corrupted clock signals. This post describes the challenges of clock network and clock jitter analysis in more ...
Hypebeast

Braun & NEIGHBORHOOD Reproduce Retro Clock Designs From the 1980s

Set for release of June 7, NEIGHBORHOOD and German electronics manufacturer Braun are reproducing an alarm clock and a wall clock originally designed in the 1980s. The collection centers on ...
Embedded

Dealing with PLL clock jitter in advanced processor designs: Part 3

Before we discuss the guidelines that the developer must follow when measuring TIE jitter, it is useful to also look at jitter for a much more general case in which jitter is not assumed to be ...
Electronic Design

Clock-Tree Tool Supports Internet Infrastructure Designs

An online timing tool crafted by Silicon Labs eases clock-tree design for Internet infrastructure applications. The Clock Tree Expert tool enables fast generation of sophisticated, streamlined ...
Semiconductor Engineering

Streamlining DO-254 Compliance: The Power Of Automated Clock-Domain Crossing Verification

In the realm of safety-critical electronic hardware, particularly those governed by DO-254 compliance directives, ensuring design integrity is paramount. One of the most insidious challenges designers ...
Embedded

FPGA Clock Schemes

One of the most important steps in the design process is to identify how many different clocks to use and how to route them. This article tells you how to use routing resources efficiently.
gearpatrol

Your Next Timepiece Purchase: This Analog Alarm Clock

You’d be surprised how much junk email you get as an editor in the form of pitches from PR agencies that aren’t remotely relevant to your vertical. I mean, I get that some CRM is mechanically and ...