Last month we put the ‘R’ into RTL by discussing registers and how to create them in Verilog and VHDL. We learned how to create resets, both synchronous and asynchronous, clock enables, and even…clock ...

While it is tempting to write RTL and let the synthesis tool take over, this isn’t the best way to get the results we want. In this article, we’ll learn how to create complex combinatorial code in ...