EDN

ESD target levels: Impacting ESD from components to systems

The Industry Council on ESD Target Levels, since its inception in 2006, has strongly influenced the IC industry’s ESD qualification processes. The industry’s original ESD qualification requirements ...
EDN

Transistor level ESD verification in large SoC designs

When it comes to large system-on-chip (SoC) designs, there is a need for a comprehensive electrostatic discharge (ESD) verification flow that can verify both topological and geometrical constructions ...
Business Wire

Apache Introduces PathFinder, the Industry’s First Full-chip ESD Physical Integrity Solution

SAN JOSE, Calif.--(BUSINESS WIRE)--Apache Design Solutions, the technology leader in power integrity and noise closure for chip-package-systems (CPS) convergence, today announced PathFinder™, a ...
Semiconductor Engineering

Can We Efficiently Automate 2.5/3D IC ESD Protection Verification?

Protection against ESD events (commonly referred to as ESD robustness) is an extremely important aspect of integrated circuit (IC) design and verification, including 2.5/3D designs. ESD events cause ...
Semiconductor Engineering

Assessing ESD Sensitivity Of Interface IP Using Charged Device Model

An electronic device is susceptible to Electrostatic Discharge (ESD) damage during its entire life cycle, especially from the completion of the silicon wafer processing to when the device is assembled ...
Design-Reuse

Testable SoCs : Every new design is an ESD test chip

The effect of low ESD immunity on a new product introduction can be both obvious and subtle. Manufacturing and test facilities adhere to ANSI standards for ESD protection and handling of chips based ...