EDN

ESD target levels: Impacting ESD from components to systems

The Industry Council on ESD Target Levels, since its inception in 2006, has strongly influenced the IC industry’s ESD qualification processes. The industry’s original ESD qualification requirements ...
EDN

Transistor level ESD verification in large SoC designs

When it comes to large system-on-chip (SoC) designs, there is a need for a comprehensive electrostatic discharge (ESD) verification flow that can verify both topological and geometrical constructions ...
Business Wire

Apache Introduces PathFinder, the Industry’s First Full-chip ESD Physical Integrity Solution

SAN JOSE, Calif.--(BUSINESS WIRE)--Apache Design Solutions, the technology leader in power integrity and noise closure for chip-package-systems (CPS) convergence, today announced PathFinder™, a ...
Semiconductor Engineering

Assessing ESD Sensitivity Of Interface IP Using Charged Device Model

An electronic device is susceptible to Electrostatic Discharge (ESD) damage during its entire life cycle, especially from the completion of the silicon wafer processing to when the device is assembled ...
Semiconductor Engineering

Context-Aware SPICE Simulation Improves The Fidelity Of ESD Analysis

Electrostatic discharge (ESD) is a major reliability concern for integrated circuit (IC) designs. ESD verification is proving to be a significant challenge at advanced nodes, due to growing IC design ...