电子工程专辑

AMD FPGA搭配ISSI DDR4设计指南

MIG IP(Memory Interface Generator,存储器接口生成器)是AMD公司为其FPGA产品开发的一款专用IP核,主要用于简化FPGA与外部高速存储器之间接口的设计与实现。 AMD FPGA MIG IP作用: MIG IP作用是自动生成符合存储器规范的接口逻辑,帮助开发者快速构建稳定\高性能的存储器连接,而 ...
Design-Reuse

Xilinx Solves Memory Interface Design Challenges With Virtex-4 Memory Development System

Easiest-to-use memory solution with unique ChipSync source synchronous circuitry cuts design time and provides industry's highest bandwidth SAN JOSE, Calif., November 9, 2004 - Xilinx Inc. (NASDAQ: ...
EDN

Xilinx simplifies memory interface designs with complete FPGA solutions

Xilinx has announced immediate availability of its low cost Spartan-3A FPGA development kit for DDR2 SDRAM interfaces, the Virtex-5 FPGA development platform (ML-561) for multiple high-performance ...
EDN

Xilinx simplifies memory interface designs

San Jose, Calif.—Xilinx Inc. announced immediate availability of its low-cost Spartan-3A FPGA development kit for DDR2 SDRAM interfaces, the Virtex-5 FPGA development platform (ML-561) for multiple ...
Design-Reuse

How to build reliable FPGA memory interface controllers without writing your own RTL code!

What if a designer could simply use a GUI to input the memory system parameters and generate RTL code for use in an FPGA without writing it from scratch? As FPGA designers strive to achieve higher ...