EDN

I/O planning, floor-plan synthesis go hand in hand

Even though companies sell packaged devices and not bare chips, the chips are often designed in isolation and may be either overdesigned or too large to fit the package. When chip-level I/O planning ...
EDN

Mastering the I/O planning puzzle

Systemwide I/O planning is an exercise in coordinating device placement with associated pin and net assignments across the chip-package-board system to maximize system quality for the target ...
mccormick.northwestern.edu

Microprocessor System Design Students Demo Final Projects

Integrating processors, sensors, and data exchange functionality into everyday objects, the Internet of Things (IoT) pushes computing capabilities far beyond desktops and servers. On December 5, ...
Electronic Design

I/O Fabric Generator Spins Complex SoC Designs

The Spinner I/O fabric generation tool for automated, bug-free I/O fabric synthesis of complex SoCs is said to automatically generate and validate the RTL for the complete I/O layer of an IC from a ...
Design-Reuse

Rambus India High-Speed I/O Design Team Achieves First Silicon Success; TSMC 90nm PCI Express* 2.5Gbps design fully characterized and compliant to specification

TSMC 90nm PCI Express* 2.5Gbps design fully characterized and compliant to specification Los Altos, California, United States - November 20, 2006 -- Rambus Inc. (Nasdaq: RMBS), one of the world's ...
IEEE

Mark Papermaster

Mark Papermaster is chief technology officer and senior vice president of Technology and Engineering at AMD, responsible for corporate technical direction, product development including system-on-chip ...