Semiconductor Engineering

Multi-Core Architecture Optimized For Time-Predictable Neural Network Inference (FZI, KIT)

A new technical paper titled “MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference” was published by researchers at FZI Research Center for Information ...
Semiconductor Engineering

TU Dresden: Tile-based Multi-Core Architecture for Heterogeneous RISC-V Processors Suitable ...

New technical paper titled “AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors” from researchers at Technische Universitaet Dresden (TU Dresden). “In this work, ...