SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that its PHY and Controller IP for the PCI Express ® (PCIe ®) 5.0 specification in the TSMC N7, N6 and N5 ...

PCI-SIG, the consortium that is in charge of developing and maintaining the PCI Express standard, announced a couple of developments this week. One is the official launch of the PCIe 4.0 specification ...

Intel's Rocket Lake could deliver the largest uplift in chipset capabilities that we've seen in quite some time -- as well as a new CPU architecture despite the fact that RLK is still a 14nm part.

The PEX 8517 PCIe switch IC has a streamlined second-generation switching architecture with five ports and 16 lanes. The device features 150-ns latency, improved throughput, reduced per-port costs, ...

Intel's Rocket Lake could deliver the largest uplift in chipset capabilities that we've seen in quite some time -- as well as a new CPU architecture despite the fact that RLK is still a 14nm part.

SAN JOSE, Calif.--(BUSINESS WIRE)--PLDA, the industry leader in PCI Express® and interface IP solutions and M31, a global silicon intellectual property (IP) boutique, today announced that their ...

The Peripheral Component Interconnect (PCI) architecture has been the cornerstone for I/O connectivity in computing, communication, and storage platforms for more than two decades. What started off as ...