The AD9577 provides a multioutput clock generator function along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on ...

Before we discuss the guidelines that the developer must follow when measuring TIE jitter, it is useful to also look at jitter for a much more general case in which jitter is not assumed to be ...

The NB4N507A is the first in a series of fully-integrated phase lock loop (PLL) ICs designed to replace expensive crystal oscillators for clock generation in a wide variety of consumer and networking ...