There is considerable ongoing discussion on how to contain exponentially increasing test costs for systems-on-chip (SoCs) and microprocessors. As the transistor geometry shrinks and more transistors ...

Testing multiple devices at the same time is not providing the equivalent reduction in overall test time due to a combination of test execution issues, the complexity of the devices being tested, and ...

Time is money in electronics, as in other industries, and the more time that is invested in testing chips means more costs being added to the product in question. To speed up testing for memory ...

Increased device complexity can be addressed by providing parallel test while decreasing the throughput overhead of the ATE architecture. The consumer world is converging, and the lines between ...