TAIPEI, Taiwan--(BUSINESS WIRE)--TrendForce reports that the three largest DRAM suppliers are increasing wafer input for advanced processes. Following a rise in memory contract prices, companies have ...

Asymmetries in wafer map defects are usually treated as random production hardware defects. For example, asymmetric wafer defects can be caused by particles inadvertently deposited on a wafer during ...

Researchers from China's Shandong University have proposed a new methodology for the quantitative prediction of excess kerf loss caused by lateral vibration of diamond wire wafer cutting in solar ...

Detecting macro-defects early in the wafer processing flow is vital for yield and process improvement, and it is driving innovations in both inspection techniques and wafer test map analysis. At the ...

NexWafe GmbH (NexWafe) has established a U.S. subsidiary to evaluate the development of multi-gigawatt-scale solar wafer production in the U.S. with an initial target production volume of six ...

TL;DR: TSMC is set to begin high-volume production of its advanced N2 (2nm-class) process node with gate-all-around nanosheet transistors in late 2025, delivering up to 15% better performance or 30% ...

In a new weekly update for pv magazine, OPIS, a Dow Jones company, provides a quick look at the main price trends in the global PV industry. FOB China prices for wafers have experienced a widespread ...

Every Wednesday and Friday, TechNode’s Briefing newsletter delivers a roundup of the most important news in China tech, straight to your inbox. Sign up As TSMC prepares to begin 4nm mass production at ...

Chosun Biz and ICSmart report that Samsung Electronics plans to reduce NAND wafer production at its Xi'an factory in China by over 10%. Amid a global NAND oversupply, this decision likely aims to ...

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