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CMOS异或门仿真设计
异或门 (简称XOR gate)是数字逻辑中实现逻辑异或的逻辑门。有多个输入端、一个输出端,多输入异或门可由两输入异或门构成。若两个输入的电平相异,则输出为高电平1;若两个输入的电平相同,则输出为低电平0。即如果两个输入不同,则异或门输出高电平1。
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