This paper designs an 8:1 multiplexer with CMOS Transmission Gate Logic (TGL) using the power gating technique, which reduces the leakage power and leakage current in active mode.

The NAND gate is a circuit that outputs '0' when both inputs are '1', and '0' otherwise, so if you arrange the NAND gate as follows, the Invert circuit is completed.

With the two diodes reversed and a 910 Ohm resistor removed, a NOR gate is created. The next step was to build a S-R latch using the NAND gates and inverters, which holds some basic memory.

NAND and NOR gates demonstrated by spin waves using magnetic oxides Home > Press Releases. JST Press Release. August 11 ... Takagi, Yuichi Nakamura, Hironaga Uchida and Mitsuteru Inoue. “The role of ...