Abstract: For designing embedded computer architectures that meet desired performance constraints at low cost, fast and accurate simulation models are needed early in the design flow. To identify and ...

Abstract: This paper presents a tutorial on the Tracking, Telemetry, and Command (TT&C) for spacecraft and satellite missions. In particular, it provides a thorough summary of the design of the TT&C, ...

High-level synthesis (HLS) continues to grow in favor among beleaguered system-on-a-chip (SoC) design teams. At the same time, EDA vendors continue to increase the capabilities of their tools. The ...

High-level synthesis (HLS) is a design flow in which design intent is described at a higher level of abstraction than RTL, such as in SystemC/C++ or MATLAB. HLS tools are expected to synthesize this ...

Formally checking generated RTL can be difficult to analyze as errors cannot be correlated to the HLS source code. Questa HLV can help overcome this challenge with high-level verification. Siemens ...