Abstract: An in-array Build-In Self-Test (BIST) scheme is proposed for the embedded SRAM array. The linear feedback shift register (LFSR) is used to implement the pattern generator, and the ...

Abstract: A 15-transistor (15T) SRAM cell-based fully-digital computing-in-memory (CIM) macro is proposed for artificial intelligence accelerations. The CIM macro not only supports simultaneous read + ...